The present invention relates generally to pipeline computers.
Current high-performance data processing systems are usually equipped with a plurality of pipelined arithmetic and logic functions which are executed in machine cycles. When arithmetic operations of identical type are executed, operands are continuously supplied to a particular arithmetic unit, while at the same time, arithmetic/logic operations of different types may be executed in a parallel mode by different arithmetic/logic units. A memory access controller is provided to fetch data from the main memory in response to a memory access instruction. The results of arithmetic/logic instructions and data from the memory access controller are written into general registers. If no conflict occurs on the write path of the general registers, each instruction can be executed within a machine cycle.
However, such resource-usage conflicts often occur due to different execution times. A contention check circuit is therefore provided for queuing contending requests through buffer registers to avoid resource-usage conflict. The memory access controller is usually provided with a cache memory to enable it to write data into a general register within a specified time interval if a cache memory "hit" occurs if the data to be fetched is found therein. If the data to be found in the cache memory is not present (cache memory miss), it takes much longer than the specified time interval for writing data into general registers. Another contention check circuit is therefore provided to acquire the right to access general registers at the instant a data item is fetched from the main memory. Therefore, the current pipelined data processing system suffers from hardware complexity and reduced throughput.